Computer Organization and Architecture Mcqs

Page No. 36

The duration between the read and the mfc signal is ______


aAccess time

✓


bLatency

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cDelay

✖


d Cycle time

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View Answer Access time

The block transfer capability of the DRAM is called ________


aBurst mode

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bBlock mode

✖


cFast page mode

✓


dFast frame mode

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View Answer Fast page mode

In order to read multiple bytes of a row at the same time, we make use of ______


aLatch

✓


bShift register

✖


cCache

✖


dMemory extension

✖


View Answer Latch

To get the row address of the required data ______ is enabled.


aCAS

✖


bRAS

✓


cCS

✖


d Sense/write

✖


View Answer RAS

The processor must take into account the delay in accessing the memory location, such memories are called ______


aDelay integrated

✖


bAsynchronous memories

✓


cSynchronous memories

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dIsochronous memories

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View Answer Asynchronous memories

To reduce the number of external connections required, we make use of ______


aDe-multiplexer

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bMultiplexer

✓


cEncoder

✖


dDecoder

✖


View Answer Multiplexer

_________ circuit is used to restore the capacitor value.


a Sense amplify

✓


bSignal amplifier

✖


cDelta modulator

✖


dNone of the mentioned

✖


View Answer Sense amplify

The capacitors lose the charge over time due to ________


aThe leakage resistance of the capacitor

✓


bThe small current in the transistor after being turned on

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cThe defect of the capacitor

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dNone of the mentioned

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The reason for the cells to lose their state over time is ________


aThe lower voltage levels

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bUsage of capacitors to store the charge

✓


c Use of Shift registers

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dNone of the mentioned

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The disadvantage of DRAM over SRAM is/are _______


aLower data storage capacities

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bHigher heat dissipation

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cThe cells are not static

✓


dAll of the mentioned

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