Computer Organization and Architecture Mcqs

Page No. 35

A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organized into _____


a128 X 8

✖


b256 X 4

✖


c512 X 2

✖


d1024 X 1

✓


View Answer 1024 X 1

A 16 X 8 Organisation of memory cells, can store upto _____


a256 bits

✖


b1024 bits

✖


c512 bits

✖


d128 bits

✓


View Answer 128 bits

The word line is driven by the _____


aChip select

✖


bAddress decoder

✓


cData line

✖


dControl line

✖


View Answer Address decoder

The cells in each column are connected to ______


a Word line

✖


bData line

✖


cRead line

✖


dSense/ Write line

✓


View Answer Sense/ Write line

The cells in a row are connected to a common line called ______


aWork line

✖


bWord line

✓


cLength line

✖


dPrinciple diagonal

✖


View Answer Word line

VLSI stands for ___________


aVery Large Scale Integration

✓


bVery Large Stand-alone Integration

✖


cVolatile Layer System Interface

✖


dNone of the mentioned

✖



The logical addresses generated by the cpu are mapped onto physical memory by ____________


aRelocation register

✖


bTLB

✖


cMMU

✓


dNone of the mentioned

✖


View Answer MMU

__________ is the bottleneck, when it comes computer performance.


aMemory access time

✖


bMemory cycle time

✓


cDelay

✖


dLatency

✖


View Answer Memory cycle time

MFC is used to _________


aIssue a read signal

✖


bSignal to the device that the memory read operation is complete

✖


cSignal the processor the memory operation is complete

✓


dAssign a device to perform the read operation

✖



The minimum time delay between two successive memory read operations is ______


aCycle time

✓


bLatency

✖


cDelay

✖


dNone of the mentioned

✖


View Answer Cycle time

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