Computer Organization and Architecture Mcqs

Page No. 15

The advantage of I/O mapped devices to memory mapped is ___________


aThe former offers faster transfer of data


bThe devices connected using I/O mapping have a bigger buffer space


cThe devices have to deal with fewer address lines


dNo advantage as such



In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.


aFalse


bTrue


ceither true either false


dnone of the mentioned


View Answer True

The usual BUS structure used to connect the I/O devices is ___________


aStar BUS structure


bMultiple BUS structure


cSingle BUS structure


dNode to Node BUS structure


View Answer Single BUS structure

In memory-mapped I/O ____________


aThe I/O devices and the memory share the same address space


bThe I/O devices have a separate address space


cThe memory and I/O devices have an associated address space


dA part of the memory is specifically set aside for the I/O operation



How can the processor ignore other interrupts when it is servicing one ___________


aBy turning off the interrupt request line


bBy disabling the devices from sending the interrupts


cBY using edge-triggered request lines


dAll of the mentioned


View Answer All of the mentioned

From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer. i) Bulk transfer of several kilo-byte ii) Moderately large data transfer of more than 1kb iii) Short events like mouse action iv) Keyboard inputs


ai and ii


bii


ci, ii and iv


div


View Answer iv

Which interrupt is unmaskable?


aRST 5.5


bRST 7.5


cTRAP


dBoth RST 5.5 and 7.5


View Answer TRAP

CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged.


aA hardware interrupt is needed


bA software interrupt is needed


cEither hardware or software interrupt is needed


dA non-privileged instruction (which does not generate an interrupt)is needed



The 8085 microprocessor responds to the presence of an interrupt ___________


aAs soon as the trap pin becomes ‘LOW’


bBy checking the trap pin for ‘high’ status at the end of each instruction fetch


cBy checking the trap pin for ‘high’ status at the end of execution of each instruction


dBy checking the trap pin for ‘high’ status at regular intervals



An interrupt that can be temporarily ignored is ___________


aVectored interrupt


b Non-maskable interrupt


cMaskable interrupt


dHigh priority interrupt


View Answer Maskable interrupt

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